1. Technical Field
The invention disclosed broadly relates to integrated circuit technology and more particular relates to an improved scaled BiCMOS circuit.
2. Background Art
As BiCMOS technology scales to smaller physical dimensions, so does the maximum power supply voltage V.sub.dd for reliable circuit operation. For example, a one micron BiCMOS technology will support 5 volts across the MOS devices, but in a one-fourth micron BiCMOS technology circuit power supply volta V.sub.dd is limited to approximately 2.5 volts. At lower power supply levels the performance of the conventional BiCMOS circuit of FIG. 1 fails to keep pace with the improvements which can be realized by the FET devices themselves. This occurs because the bipolar transistor V.sub.BE does not get smaller when the physical dimensions of the bipolar devices are reduced. The large V.sub.BE of the bipolar transistor delays and reduces the input drive of the circuit because less of the input signal is available as overdrive.
Furthermore, the conventional BiCMOS circuit of FIG. 1 fails to provide a full V.sub.dd level when the output is high. This results in an inferior noise margin, and makes it difficult or even impossible to use the circuit when it is desired to mix it with conventional CMOS circuit functions on the same integrated circuit chip.
A circuit that overcomes one of the limitations of the circuit of FIG. 1 is disclosed in FIG. 2. This circuit achieves good performance at low power supply voltages, but it is not CMOS compatible. This circuit achieves a performance gain by operating it from a power supply which is higher by one V.sub.BE than the V.sub.dd of the circuit shown in FIG. 1. This configuration does not impose any additional voltage stress on any of the FET devices even though the power supply is higher. Output clamping devices have been included to render the circuit insensitive to noise coupled to the output line.
Diode connected bipolar transistor Q4 raises the FET sources by a voltage V.sub.BE. The standard output down-level is V.sub.BE instead of ground, and the output up-level is V.sub.dd minus V.sub.BE. Circuit performance is improved over conventional designs because the drive level is increased.
Bipolar device Q3 acts as a clamp to prevent a down level output from being driven negatively into a high impedance condition by noise on the output line. Likewise, bipolar device Q5 clamps the output to V.sub.dd minus V.sub.BE in the output up-level state when noise would otherwise act to drive the circuit upward into a high impedance condition. Such excursions would otherwise overstress some of the FET devices for long periods of time under certain operational conditions. Under normal conditions Q3 lightly conducts when the circuit output is a down-level, and Q5 lightly conducts when the circuit output is an up-level. The amount of conduction depends upon the setting of the reference voltages VR1 and VR2. Noise causes the clamp devices to conduct heavily, absorbing the energy and quickly clamping the output voltage. Reference voltages VR1 and VR2 are readily generated by conventional circuit means, and will typically be shared by several circuits on a chip.
In an all-BiCMOS circuit environment this circuit will work reasonably well, but it does not interface directly with conventional CMOS circuits which may be on the same chip.